Normally an integrated circuit layout is performed by drawing polygons which is a time consuming process that must be repeated for each process. In this type of layout system components consisting of polygons are placed in a pattern. This pattern will represent a circuit. In order to represent a circuit, polygons on several different layers are used. The types of layers include active, poly, contact and metal layers. By placing these layers next to each other or on top of each other, a circuit layout can be achieved.
In an integrated circuit layout there are a variety of ways in which the transistors and wiring can be arranged. A particular style of integrated circuit layout can be called an architecture. FIG. 1 illustrates an example of an architecture 10 is placing transistors parallel to each other.
The above-identified process is adequate for creating integrated circuit layout utilizing a particular process. However, this type of layout is not easily ported from a reference process to a target process. Known tools to migrate an integrated circuit layout from a reference process to a target process do not preserve the general topology of the cell. This is especially important when the cells are used in an automatic place and route flow. What is needed is a system and method for porting an integrated circuit layout from a reference process to a target process. The system must be easily implemented, cost effective and easily adaptable to existing systems.
The present invention addresses such a need.